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1 ltc1852/ltc1853 18523f block diagra w applicatio s u features descriptio u 8-channel, 10-bit/12-bit, 400ksps, low power, sampling adcs the 10-bit ltc ? 1852 and 12-bit ltc1853 are complete 8-channel data acquisition systems. they include a flex- ible 8-channel multiplexer, a 400ksps successive approxi- mation analog-to-digital converter, an internal reference and a parallel output interface. the multiplexer can be configured for single-ended or differential inputs, two gain ranges and unipolar or bipolar operation. the adcs have a scan mode that will repeatedly cycle through all 8 multiplexer channels and can also be programmed to sequence through up to 16 addresses and configurations. the sequence can also be read back from internal memory. the reference and buffer amplifier provide pin strappable ranges of 4.096v, 2.5v and 2.048v. the parallel output includes the 10-bit or 12-bit conversion result plus the 4- bit multiplexer address. the digital outputs are powered from a separate supply allowing for easy interface to 3v digital logic. typical power consumption is 10mw at 400ksps from a single 5v supply and 3mw at 250ksps from a single 3v supply. n flexible 8-channel multiplexer single-ended or differential inputs two gain ranges unipolar or bipolar operation n scan mode and programmable sequencer eliminate configuration software overhead n low power: 3mw at 250ksps n 2.7v to 5.5v supply range n internal or external reference operation n parallel output includes mux address n nap and sleep shutdown modes n pin compatible up-grade 1.25msps 10-bit ltc1850 and 12-bit ltc1851 n high speed data acquisition n test and measurement n imaging systems n telecommunications n industrial process control n spectrum analysis busy diff out /s6 a2 out /s5 a1 out /s4 a0 out /s3 d11/s2 d10/s1 d9/s0 d8 d7 d6 d5 d4 d3 d2 d1 d0 m1 shdn cs convst rd wr diff a2 a1 a0 uni/bip pga m0 output drivers data latches ognd 18523 bd ov dd ref amp refcomp refin refout com ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 8-channel multiplexer 2.5v reference internal clock ltc1853 control logic and programmable sequencer 12-bit sampling adc + , ltc and lt are registered trademarks of linear technology corporation. integral linearity 0 512 1024 1536 2048 2560 3072 3584 4096 code 1.0 0.5 0 0.5 ?.0 inl error (lsbs) 1852 f01
2 ltc1852/ltc1853 18523f a u g w a w u w a r b s o lu t exi t i s ov dd = v dd (notes 1, 2) supply voltage (v dd ) ................................................. 6v analog input voltage (note 3) ..... C 0.3v to (v dd + 0.3v) digital input voltage (note 4) ....................C 0.3v to 10v digital output voltage .................. C 0.3v to (v dd + 0.3v) power dissipation .............................................. 500mw wu u package / o rder i for atio order part number ltc1853cfw ltc1853ifw t jmax = 150 c, q ja = 110 c/w 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 top view fw package 48-lead plastic tssop 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com refout refin refcomp gnd v dd v dd gnd diff out /s6 a2 out /s5 a1 out /s4 a0 out /s3 d11/s2 d10/s1 d9/s0 d8 m1 shdn cs convst rd wr diff a2 a1 a0 uni/bip pga m0 ov dd ognd busy d0 d1 d2 d3 d4 d5 d6 d7 consult ltc marketing for parts specified with wider operating temperature ranges. order part number ltc1852cfw LTC1852IFW t jmax = 150 c, q ja = 110 c/w 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 top view fw package 48-lead plastic tssop 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com refout refin refcomp gnd v dd v dd gnd diff out /s6 a2 out /s5 a1 out /s4 a0 out /s3 d9/s2 d8/s1 d7/s0 d6 m1 shdn cs convst rd wr diff a2 a1 a0 uni/bip pga m0 ov dd ognd busy nc nc d0 d1 d2 d3 d4 d5 ambient operating temperature range ltc1852c/ltc1853c ............................ 0 c to 70 c ltc1852i/ltc1853i .......................... C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec)................ 300 c
3 ltc1852/ltc1853 18523f symbol parameter conditions min typ max units v in analog input range (note 9) 2.7v v dd 5.5v, refcomp v dd unipolar, gain = 1 (pga = 1) 0 C refcomp v unipolar, gain = 2 (pga = 0) 0 C refcomp/2 v bipolar, gain = 1 (pga = 1) refcomp/2 v bipolar, gain = 2 (pga = 0) refcomp/4 v i in analog input leakage current l 1 m a c in analog input capacitance between conversions (gain = 1) 15 pf between conversions (gain = 2) 25 pf during conversions 5 pf t acq sample-and-hold acquisition time 50 150 ns t s(mux) multiplexer settling time (includes t acq ) 50 150 ns t ap sample-and-hold aperture delay time v dd = 5v C 0.5 ns t jitter sample-and-hold aperture delay time jitter v dd = 5v 2 ps rms cmrr analog input common mode rejection ratio 60 db ltc1852 ltc1853 parameter conditions min typ max min typ max units resolution (no missing codes) l 10 12 bits integral linearity error (note 7) l 0.25 1 0.35 1lsb differential linearity error l 0.25 1 0.25 1lsb offset error (bipolar and unipolar) (note 8) gain = 1 (pga = 1) refcomp 3 2v l 0.5 2 1 6lsb gain = 2 (pga = 0) l 1 4 2 12 lsb offset error match (bipolar and unipolar) 0.5 1lsb unipolar gain error with external 4.096v reference gain = 1 (pga = 1) applied to refcomp (note 12) 2 4lsb gain = 2 (pga = 0) v dd = 4.75v to 5.25v, f s 400khz 4 8lsb unipolar gain error match 0.5 1lsb bipolar gain error with external 4.096v reference gain = 1 (pga = 1) applied to refcomp (note 12) 2 4lsb gain = 2 (pga = 0) v dd = 4.75v to 5.25v, f s 400khz 4 8lsb bipolar gain error match 0.5 1lsb unipolar gain error with external 2.5v reference gain = 1 (pga = 1) applied to refcomp l 1 3 1.5 8lsb gain = 2 (pga = 0) v dd = 2.7v to 5.5v, f s 250khz l 2 6 3 16 lsb bipolar gain error with external 2.5v reference gain = 1 (pga = 1) applied to refcomp l 1 3 1.5 8lsb gain = 2 (pga = 0) v dd = 2.7v to 5.5v, f s 250khz l 2 6 3 16 lsb full-scale error temperature coefficient 15 15 ppm/ c the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) a alog i put u u the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v dd = 2.7v to 5.5v, refcomp < v dd (notes 5, 6) co verter characteristics u symbol parameter conditions min typ max units s/(n + d) signal-to-noise plus distortion ratio 40khz input signal 72.5 db thd total harmonic distortion 40khz input signal, first 5 harmonics C80 db sfdr spurious free dynamic range 40khz input signal C85 db dy a ic accuracy u w t a = 25 c. (note 5)
4 ltc1852/ltc1853 18523f parameter conditions min typ max units refout output voltage i out = 0 2.48 2.50 2.52 v refout output temperature coefficient i out = 0 15 ppm/ c refout line regulation 2.7 v dd 5.5, i out = 0 0.01 lsb/v reference buffer gain 1.6368 1.6384 1.6400 v/v refcomp output voltage external 2.5v reference (v dd = 5v) 4.092 4.096 4.100 v internal 2.5v reference (v dd = 5v) 4.060 4.096 4.132 v refcomp impedance impedance to gnd, refin = v dd 19.2 k w t a = 25 c. (notes 5, 6) i ter al refere ce uu u the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v dd = 5v (note 5) digital i puts a d digital outputs u u symbol parameter conditions min typ max units v ih high level input voltage v dd = 3.3v l 1.9 v v il low level input voltage v dd = 2.7v l 0.45 v i in digital input current v in = 0v to v dd l 5 m a c in digital input capacitance 1.5 pf v oh high level output voltage v dd = 2.7v, i o = C10 m a 2.5 v v dd = 2.7v, i o = C 200 m a l 2v v ol low level output voltage v dd = 2.7v, i o = 160 m a 0.05 v v dd = 2.7v, i o = 1.6ma l 0.10 0.4 v i oz hi-z output leakage d11 to d0, a0, a1, a2 out , diff out v out = 0v to v dd , cs high l 10 m a c oz hi-z capacitance d11 to d0 cs high (note 9) l 15 pf i source output source current v out = 0v C 10 ma i sink output sink current v out = v dd 15 ma the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v dd = 3v (note 5) digital i puts a d digital outputs u u symbol parameter conditions min typ max units v ih high level input voltage v dd = 5.25v l 2.4 v v il low level input voltage v dd = 4.75v l 0.8 v i in digital input current v in = 0v to v dd l 5 m a c in digital input capacitance 1.5 pf v oh high level output voltage v dd = 4.75v, i o = C10 m a 4.5 v v dd = 4.75v, i o = C 200 m a l 4v v ol low level output voltage v dd = 4.75v, i o = 160 m a 0.05 v v dd = 4.75v, i o = 1.6ma l 0.10 0.4 v i oz hi-z output leakage d11 to d0, a0, a1, a2 out , diff out v out = 0v to v dd , cs high l 10 m a c oz hi-z capacitance d11 to d0 cs high (note 9) l 15 pf i source output source current v out = 0v C 20 ma i sink output sink current v out = v dd 30 ma
5 ltc1852/ltc1853 18523f symbol parameter conditions min typ max units f sample(max) maximum sampling frequency v dd = 5.5v l 400 khz v dd = 2.7v l 250 khz acquisition + conversion v dd = 5.5v l 2.5 m s v dd = 2.7v l 4.0 m s t conv conversion time v dd = 5.5v l 2.0 m s v dd = 2.7v l 3.5 m s t acq acquisition time (note 13) l 150 ns t 1 cs to rd setup time (notes 9, 10) l 0ns t 2 cs to convst setup time (notes 9, 10) l 10 ns t 3 cs to shdn setup time (notes 9, 10) 200 ns t 4 shdn to convst wake-up time nap mode (note 10) 200 ns sleep mode (note 10) 10 ms t 5 convst low time (notes 10, 11) l 50 ns t 6 convst to busy delay c l = 25pf 10 ns l 60 ns t 7 data ready before busy 20 35 ns l 15 ns t 8 delay between conversions (note 10) l 50 ns t 9 wait time rd after busy l C5 ns t 10 data access time after rd c l = 25pf 20 35 ns l 45 ns c l = 100pf 25 45 ns l 60 ns t 11 bus relinquish time 10 30 ns 0 c to 70 c l 35 ns C40 c to 85 c l 40 ns symbol parameter conditions min typ max units v dd analog positive supply voltage (note 10) l 2.7 5.5 v ov dd output positive supply voltage (note 10) l 2.7 5.5 v i dd positive supply current v dd = ov dd = 5v, f s = 400khz l 23ma v dd = ov dd = 2.7v, f s = 250khz l 0.83 1.33 ma p diss power dissipation v dd = ov dd = 5v, f s = 400khz l 10 15 mw v dd = ov dd = 2.7v, f s = 250khz l 2.25 4 mw i ddpd power down positive supply current nap mode shdn = low, cs = low 0.5 ma sleep mode shdn = low, cs = high 20 m a power down power dissipation v dd = v dd = ov dd = 5v, f s = 400khz nap mode shdn = low, cs = low 2.5 mw sleep mode shdn = low, cs = high 0.1 mw power down power dissipation v dd = v dd = ov dd = 3v, f s = 250khz nap mode shdn = low, cs = low 1.5 mw sleep mode shdn = low, cs = high 0.06 mw the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) power require e ts w u the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) ti i g characteristics u w
6 ltc1852/ltc1853 18523f symbol parameter conditions min typ max units t 12 rd low time l t 10 ns t 13 convst high time (note 10) l 50 ns t 14 latch setup time (note 10) l 10 ns t 15 latch hold time (notes 9, 10) l 10 ns t 16 wr low time (note 10) l 50 ns t 17 wr high time (note 10) l 50 ns t 18 m1 to m0 setup time (notes 9, 10) l 10 ns t 19 m0 to busy delay m1 high 20 ns t 20 m0 to wr (or rd) setup time (notes 9, 10) l t 19 ns t 21 m0 high pulse width (note 10) l 50 ns t 22 rd high time between readback reads (note 10) l 50 ns t 23 last wr (or rd) to m0 (note 10) l 10 ns t 24 m0 to rd setup time (notes 9, 10) l t 19 ns t 25 m0 to convst (note 10) l t 19 ns t 26 aperture delay C 0.5 ns t 27 aperture jitter 2ps rms the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) ti i g characteristics u w note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to ground with ognd and gnd wired together unless otherwise noted. note 3: when these pin voltages are taken below ground or above v dd , they will be clamped by internal diodes. this product can handle input currents of 100ma below ground or above v dd without latchup. note 4: when these pin voltages are taken below ground, they will be clamped by internal diodes. this product can handle input currents of 100ma below ground without latchup. these pins are not clamped to v dd . note 5: v dd = 5v, f sample = 400khz, t r = t f = 2ns unless otherwise specified. note 6: linearity, offset and full-scale specifications apply for a single- ended input on any channel with com grounded. note 7: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual end points of the transfer curve. the deviation is measured from the center of the quantization band. note 8: bipolar offset is the offset voltage measured from C 0.5lsb when the output code flickers between 1111 1111 1111 and 0000 0000 0000. for the ltc1853 and between 11 1111 1111 and 00 0000 0000 for the ltc1852. note 9: guaranteed by design, not subject to test. note 10: recommended operating conditions. note 11: the falling convst edge starts a conversion. if convst returns high at a critical point during the conversion it can create small errors. for the best results, ensure that convst returns high either within 400ns after the start of the conversion or after busy rises. note 12: the analog input range is determined by the voltage on refcomp. the gain error specification is tested with an external 4.096v but is valid for any value of refcomp greater than 2v and less than (v dd C 0.5v.) note 13: mux address is updated immediately after busy falls. 1.0 0.5 0 0.5 ?.0 0 4096 code dnl error (lbs) 1852 f02 0 ?0 ?0 ?0 ?0 ?00 ?20 0200 frequency (khz) amplitude (db) 1852 f03 differential linearity 8192 point fft with f in = 39.599khz typical perfor a ce characteristics uw
7 ltc1852/ltc1853 18523f uu u pi fu ctio s ch0 to ch7 (pins 1 to 8): analog input pins. input pins can be used single ended relative to the analog input common pin or differentially in pairs (ch0 and ch1, ch2 and ch3, ch4 and ch5, ch6 and ch7). com (pin 9): analog input common pin. for single-ended operation (diff = 0), com is the C analog input. com is disabled when diff is high. refout (pin 10): internal 2.5v reference output. bypass to analog ground plane with 1 m f. refin (pin 11): reference mode select/reference buffer input. refin selects the reference mode and acts as the reference buffer input. refin tied to ground (logic 0) will produce 2.048v on the refcomp pin. refin tied to the positive supply (logic 1) disables the reference buffer to allow refcomp to be driven externally. for voltages between 1v and 2.6v, the reference buffer produces an output voltage on the refcomp pin equal to 1.6384 times the voltage on refin (4.096v on refcomp for a 2.5v input on refin). refcomp (pin 12): reference buffer output. refcomp sets the full-scale input span. the reference buffer pro- duces an output voltage on the refcomp pin equal to 1.6384 times the voltage on the refin pin (4.096v on refcomp for a 2.5v input on refin). refin tied to ground will produce 2.048v on the refcomp pin. refcomp can be driven externally if refin is tied to the positive supply. bypass to analog ground plane with 10 m f tantalum in parallel with 0.1 m f ceramic or 10 m f ceramic. gnd (pins 13, 16): ground. tie to analog ground plane. v dd (pins 14, 15): positive supply. bypass to analog ground plane with 10 m f tantalum in parallel with 0.1 m f ceramic or 10 m f ceramic. diff out /s6 (pin 17): three-state digital data output. active when rd is low. following a conversion, the single- ended/differential bit of the present conversion is available on this pin concurrent with the conversion result. in readback mode, the single-ended/differential bit of the current sequencer location (s6) is available on this pin. the output swings between ov dd and ognd. a2 out /s5, a1 out /s4, a0 out /s3 (pins 18 to 20): three- state digital mux address outputs. active when rd is low. following a conversion, the mux address of the present conversion is available on these pins concurrent with the conversion result. in readback mode, the mux address of the current sequencer location (s5-s3) is available on these pins. the outputs swing between ov dd and ognd. d9/s2 (pin 21, ltc1852): three-state digital data out- put. active when rd is low. following a conversion, bit 9 of the present conversion is available on this pin. in readback mode, the unipolar/bipolar bit of the current sequencer location (s2) is available on this pin. the output swings between ov dd and ognd. d11/s2 (pin 21, ltc1853): three-state digital data out- put. active when rd is low. following a conversion, bit 11 of the present conversion is available on this pin. in readback mode, the unipolar/bipolar bit of the current sequencer location (s2) is available on this pin. the output swings between ov dd and ognd. d8/s1 (pin 22, ltc1852): three-state digital data out- puts. active when rd is low. following a conversion, bit 8 of the present conversion is available on this pin. in readback mode, the gain bit of the current sequencer location (s1) is available on this pin. the output swings between ov dd and ognd. d10/s1 (pin 22, ltc1853): three-state digital data out- puts. active when rd is low. following a conversion, bit 10 of the present conversion is available on this pin. in readback mode, the gain bit of the current sequencer location (s1) is available on this pin. the output swings between ov dd and ognd. d7/s0 (pin 23, ltc1852): three-state digital data out- puts. active when rd is low. following a conversion, bit 7 of the present conversion is available on this pin. in readback mode, the end of sequence bit of the current sequencer location (s0) is available on this pin. the output swings between ov dd and ognd.
8 ltc1852/ltc1853 18523f d9/s0 (pin 23, ltc1853): three-state digital data out- puts. active when rd is low. following a conversion, bit 9 of the present conversion is available on this pin. in readback mode, the end of sequence bit of the current sequencer location (s0) is available on this pin. the output swings between ov dd and ognd. d6 to d0 (pins 24 to 30, ltc1852): three-state digital data outputs. active when rd is low. the outputs swing between ov dd and ognd. d8 to d0 (pins 24 to 32, ltc1853): three-state digital data outputs. active when rd is low. the outputs swing between ov dd and ognd. nc (pins 31 to 32, ltc1852): no connect. there is no internal connection to these pins. busy (pin 33): converter busy output. the busy output has two functions. at the start of a conversion, busy will go low and remain low until the conversion is completed. the rising edge may be used to latch the output data. busy will also go low while the part is in program/readback mode (m1 high, m0 low) and remain low until m0 is brought back high. the output swings between ov dd and ognd. ognd (pin 34): digital data output ground. tie to analog ground plane. may be tied to logic ground if desired. ov dd (pin 35): digital data output supply. normally tied to 5v, can be used to interface with 3v digital logic. bypass to ognd with 10 m f tantalum in parallel with 0.1 m f ceramic or 10 m f ceramic. m0 (pin 36): mode select pin 0. used in conjunction with m1 to select operating mode. see table 5. pga (pin 37): gain select input. a high logic level selects gain = 1, a low logic level selects gain = 2. uni/bip (pin 38): unipolar/bipolar select input. logic low selects a unipolar input span, a high logic level selects a bipolar input span. a0 to a2 (pins 39 to 41): mux address input pins. diff (pin 42): single-ended/differential select input. a low logic level selects single ended, a high logic level selects differential. wr (pin 43): write input. in direct address mode, wr low enables the mux address and configuration input pins (pins 37 to 42). wr can be tied low or the rising edge of wr can be used to latch the data. in program mode, wr is used to program the sequencer. wr low enables the mux address and configuration input pins (pins 37 to 42). the rising edge of wr latches the data and increments the counter to the next sequencer location. rd (pin 44): read input. during normal operation, rd enables the output drivers when cs is low. in readback mode (m1 high, m0 low), rd going low reads the current sequencer location, rd high advances to the next se- quencer location. convst (pin 45): conversion start input. this active low signal starts a conversion on its falling edge. cs (pin 46): chip select input. the chip select input must be low for the adc to recognize the convst and rd inputs. if shdn is low, a low logic level on cs selects nap mode; a high logic level on cs selects sleep mode. shdn (pin 47): power shutdown input. a low logic level will invoke the shutdown mode selected by the cs pin. cs low selects nap mode, cs high selects sleep mode. tie high if unused. m1 (pin 48): mode select pin 1. used in conjunction with m0 to select operating mode. see table 5. uu u pi fu ctio s
9 ltc1852/ltc1853 18523f uu u pi fu ctio s nominal (v) absolute maximum (v) pin name description min typ max min max 1 to 8 ch0 to ch7 analog inputs 0 v dd C 0.3 v dd + 0.3 9 com analog input common pin 0 v dd C 0.3 v dd + 0.3 10 refout 2.5v reference output 2.5 C 0.3 v dd + 0.3 11 refin reference buffer input 0 2.5 v dd C 0.3 v dd + 0.3 12 refcomp reference buffer output 4.096 C 0.3 v dd + 0.3 13 gnd ground 0 C 0.3 v dd + 0.3 14 v dd positive supply 2.7 5 5.5 C 0.3 6 15 v dd positive supply 2.7 5 5.5 C 0.3 6 16 gnd ground 0 C0.3 v dd + 0.3 17 diff out /s6 single-ended/differential output ognd ov dd C0.3 v dd + 0.3 18 a2 out /s5 mux address output ognd ov dd C0.3 v dd + 0.3 19 a1 out /s4 mux address output ognd ov dd C0.3 v dd + 0.3 20 a0 out /s3 mux address output ognd ov dd C0.3 v dd + 0.3 21 d9/s2 (ltc1852) data output ognd ov dd C0.3 v dd + 0.3 21 d11/s2 (ltc1853) data output ognd ov dd C0.3 v dd + 0.3 22 d8/s1 (ltc1852) data output ognd ov dd C0.3 v dd + 0.3 22 d10/s1 (ltc1853) data output ognd ov dd C0.3 v dd + 0.3 23 d7/s0 (ltc1852) data output ognd ov dd C0.3 v dd + 0.3 23 d9/s0 (ltc1853) data output ognd ov dd C0.3 v dd + 0.3 24 to 30 d6 to d0 (ltc1852) data outputs ognd ov dd C0.3 v dd + 0.3 24 to 32 d8 to d0 (ltc1853) data outputs ognd ov dd C0.3 v dd + 0.3 31 to 32 nc (ltc1852) no connect 33 busy converter busy output ognd ov dd C0.3 v dd + 0.3 34 ognd output ground 0 C 0.3 v dd + 0.3 35 ov dd output supply 2.7 5 5.5 C 0.3 6 36 m0 mode select pin 0 0 v dd C 0.3 6 37 pga gain select input 0 v dd C 0.3 6 38 uni/bip unipolar/bipolar input 0 v dd C 0.3 6 39 to 41 a0 to a2 mux address inputs 0 v dd C 0.3 6 42 diff single-ended/differential input 0 v dd C 0.3 6 43 wr write input, active low 0 v dd C 0.3 6 44 rd read input, active low 0 v dd C 0.3 6 45 convst conversion start input, active low 0 v dd C 0.3 6 46 cs chip select input, active low 0 v dd C 0.3 6 47 shdn shutdown input, active low 0 v dd C 0.3 6 48 m1 mode select pin 1 0 v dd C 0.3 6
10 ltc1852/ltc1853 18523f applicatio s i for atio wu uu the ltc1852/ltc1853 are complete and very flexible data acquisition systems. they consist of a 10-bit/12-bit, 400ksps capacitive successive approximation a/d con- verter with a wideband sample-and-hold, a configurable 8-channel analog input multiplexer, an internal reference and reference buffer amplifier, a 16-bit parallel digital output and digital control logic, including a programmable sequencer. conversion details t he core analog-to-digital converter in the ltc1852/ ltc1853 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 10-bit/12-bit parallel output. conversion start is controlled by the cs and convst inputs. at the start of the conversion, the successive approximation register (sar) is reset. once a conversion cycle is begun, it cannot be restarted. during the conversion, the internal differen- tial capacitive dac output is sequenced by the sar from the most significant bit (msb) to the least significant bit (lsb). the outputs of the analog input multiplexer are connected to the sample-and-hold capacitors (c sample ) during the acquire phase and the comparator offset is nulled by the zeroing switches. in this acquire phase, a minimum delay of 150ns will provide enough time for the sample-and-hold capacitors to acquire the analog signal. during the convert phase, the comparator zeroing switches are open, putting the comparator into compare mode. the input switches connect c sample to ground, transferring the differential analog input charge onto the summing junction. this input charge is successively compared with the binary weighted charges supplied by the differential ca pacitive dac. bit decisions are made by the high speed comparator. at the end of the conversion, the differential dac output balances the input charges. the sar contents (a 10-bit/12-bit data word), which represents the differ- ence of the analog input multiplexer outputs, and the 4-bit address word are loaded into the 14-bit/16-bit output latches. dynamic performance signal-to-(noise + distortion) ratio the signal-to-noise plus distortion ratio [s/(n + d)] is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the adc output. the output is band limited to frequencies above dc to below half the sampling frequency. the effective number of bits (enobs) is a measurement of the resolution of an adc and is directly related to the s/(n + d) by the equation: enob = [s/(n + d) C 1.76]/6.02 where enob is the effective number of bits and s/(n + d) is expressed in db. at the maximum sampling rate of 400khz, the ltc1852/ltc1853 maintain near ideal enobs up to and beyond the nyquist input frequency of 200khz. total harmonic distortion total harmonic distortion is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd log vvv vn v = +++ 20 234 1 222 2 ... where v1 is the rms amplitude of the fundamental frequency and v2 through vn are the amplitudes of the second through nth harmonics. the ltc1852/ltc1853 have good distortion performance up to the nyquist frequency and beyond. intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency.
11 ltc1852/ltc1853 18523f applicatio s i for atio wu uu if two pure sine waves of frequencies fa and fb are applied to the adc input, nonlinearities in the adc transfer func- tion can create distortion products at the sum and differ- ence frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. for example, the 2nd order imd terms include (fa fb). if the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order imd products can be expressed by the following formula: imd fa fb log amplitude at fa fb amplitude at fa () = () 20 peak harmonic or spurious noise the peak harmonic or spurious noise is the largest spec- tral component excluding the input signal and dc. this value is expressed in decibels relative to the rms value of a full-scale input signal. full-power and full-linear bandwidth the full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is re- duced by 3db for a full-scale input signal. the full-linear bandwidth is the input frequency at which the s/(n + d) has dropped to 68db for the ltc1853 (11 effective bits) or 56db for the ltc1852 (9 effective bits). the ltc1852/ltc1853 have been designed to optimize input bandwidth, allowing the adc to undersample input signals with frequencies above the converters nyquist frequency. the noise floor stays very low at high frequen- cies; s/(n + d) becomes dominated by distortion at frequencies far beyond nyquist. analog input multiplexer the analog input multiplexer is controlled using the single- ended/differential pin (diff), three mux address pins (a2, a1, a0), the unipolar/bipolar pin (uni/bip) and the gain select pin (pga). the single-ended/differential pin (diff) allows the user to configure the mux as eight single- ended channels relative to the analog input common pin (com) when diff is low or as four differential pairs (ch0 and ch1, ch2 and ch3, ch4 and ch5, ch6 and ch7) when diff is high. the channels (and polarity in the differential case) are selected using the mux address inputs as shown in table 1. unused inputs (including the com in the differential case) should be grounded to prevent noise coupling. table 1. multiplexer address table mux address single-ended channel selection diff a2 a1 a0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com 0000 + C 0001 + C 0010 + C 0011 + C 0100 + C 0101 + C 0110 + C 0111 + C mux address differential channel selection diff a2 a1 a0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com 1000 + C * 1001 C + * 1010 + C * 1011 C + * 1100 + C * 1101 C + * 1110 + C * 1111 C + * *not used in differential mode. connect to agnd. in addition to selecting the mux channel, the ltc1852/ ltc1853 also allows the user to select between two gains and unipolar or bipolar inputs for a total of four input spans. pga high selects a gain of 1 (the input span is equal to the voltage on refcomp). pga low selects a gain of 2 where the input span is equal to half of the voltage on refcomp. uni/bip low selects a unipolar input span, uni/bip high selects a bipolar input span. table 2 summa- rizes the possible input spans. table 2. input span table input span uni/bip pga refcomp = 4.096v 0 0 0 C refcomp/2 0 C 2.048v 0 1 0 C refcomp 0 C 4.096v 10 refcomp/4 1.024v 11 refcomp/2 2.048v
12 ltc1852/ltc1853 18523f the ltc1852/ltc1853 have a unique differential sample- and-hold circuit that allows rail-to-rail inputs. the adc will always convert the difference of the + and C inputs independent of the common mode voltage. the common mode rejection holds up to high frequencies. the only requirement is that both inputs can not exceed the av dd power supply voltage or ground. when a bipolar input span is selected the + input can swing full scale relative to the C input but neither input can exceed av dd or go below ground. integral nonlinearity errors (inl) and differential nonlin- earity errors (dnl) are independent of the common mode voltage, however, the bipolar offset will vary. the change in bipolar offset is typically less than 0.1% of the common mode voltage. some ac applications may have their performance limited by distortion. most circuits exhibit higher distortion when signals approach the supply or ground. thd will degrade as the inputs approach either power supply rail. distortion can be reduced by reducing the signal amplitude and keeping the common mode voltage at approximately midsupply. driving the analog inputs the inputs of the ltc1852/ltc1853 are easy to drive. each of the analog inputs can be used as a single-ended input relative to the input common pin (ch0-com, ch1- com, etc.) or in pairs (ch0 and ch1, ch2 and ch3, ch4 and ch5, ch6 and ch7) for differential inputs. regardless of the mux configuration, the + and C inputs are sampled at the same instant. any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sample-and-hold circuit. the inputs draw only one small current spike while charg- ing the sample-and-hold capacitors at the end of conver- sion. during conversion, the analog inputs draw only a small leakage current. if the source impedance of the driving circuit is low, then the ltc1852/ltc1853 inputs can be driven directly. as source impedance increases, so will acquisition time. for minimum acquisition time with high source impedance, a buffer amplifier should be used. the only requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be less than 150ns for full throughput rate). choosing an input amplifier choosing an input amplifier is easy if a few requirements are taken into consideration. first, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (<100 w ) at the closed-loop bandwidth frequency. for example, if an amplifier is used in a gain of +1 and has a unity-gain bandwidth of 50mhz, then the output impedance at 50mhz should be less than 100 w . the second requirement is that the closed-loop bandwidth must be greater than 10mhz to ensure adequate small- signal settling for full throughput rate. the following list is a summary of the op amps that are suitable for driving the ltc1852/ltc1853, more detailed information is available in the linear technology databooks, the linearview tm cd-rom and on our web site at www.linear-tech.com. lt ? 1360: 50mhz voltage feedback amplifier. 2.5v to 15v supplies. 5ma supply current. low distortion. lt1363: 70mhz voltage feedback amplifier. 2.5v to 15v supplies. 7.5ma supply current. low distortion. lt1364/lt1365: dual and quad 70mhz voltage feedback amplifiers. 2.5v to 15v supplies. 7.5ma supply current per amplifier. low distortion. lt1468/lt1469: single and dual 90mhz voltage feed- back amplifier. 5v to 15v supplies. 7ma supply current per amplifier. lowest noise and low distortion. lt1630/lt1631: dual and quad 30mhz rail-to-rail volt- age feedback amplifiers. single 3v to 15v supplies. 3.5ma supply current per amplifier. low noise and low distortion. lt1632/lt1633: dual and quad 45mhz rail-to-rail volt- age feedback amplifiers. single 3v to 15v supplies. 4.3ma supply current per amplifier. low distortion. lt1806/lt1807: single and dual 325mhz rail-to-rail voltage feedback amplifier. single 3v to 5v supplies. 13ma supply current. lowest distortion. applicatio s i for atio wu uu linearview is a trademark of linear technology corporation.
13 ltc1852/ltc1853 18523f lt1809/lt1810: single and dual 180mhz rail-to-rail voltage feedback amplifier. single 3v to 15v supplies. 20ma supply current. lowest distortion. lt1812/lt1813: single and dual 100mhz voltage feed- back amplifier. single 5v to 5v supplies. 3.6ma supply current. low noise and low distortion. input filtering the noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the ltc1852/ltc1853 noise and distortion. noisy input circuitry should be filtered prior to the analog inputs to minimize noise. a simple 1-pole rc filter is sufficient for many applications. for instance, a 200 w source resistor and a 1000pf capacitor to ground on the input will limit the input bandwidth to 800khz.the capacitor also acts as a charge reservoir for the input sample-and-hold and iso- lates the adc input from sampling glitch sensitive cir- cuitry. high quality capacitors and resistors should be used since these components can add distortion. npo and silver mica type dielectric capacitors have excellent linear- ity. carbon surface mount resistors can also generate distortion from self heating and from damage that may occur during soldering. metal film surface mount resistors are much less susceptible to both problems. reference the ltc1852/ltc1853 includes an on-chip, temperature compensated, curvature corrected, bandgap reference that is factory trimmed to 2.500v and has a very flexible 3- pin interface. refout is the 2.5v bandgap output, refin is the input to the reference buffer and refcomp is the reference buffer output. the input span is determined by the voltage appearing on the refcomp pin as shown in table 2. the reference buffer has a gain of 1.6384 and is factory trimmed by forcing an external 2.500v on the refin pin and trimming refcomp to 4.096v. the 3-pin interface allows for three pin-strappable reference modes as well as two additional external reference modes. for voltages on the refin pin ranging from 1v to 2.6v, the output voltage on refcomp will equal 1.6384 times the voltage on the refin pin. in this mode, the refin pin can be tied to refout to use the internal 2.5v reference to get applicatio s i for atio wu uu 4.096v on refcomp or driven with an external reference or dac. if refin is tied low, the internal 2.5v reference divided by 2 (1.25v) is connected internally to the input of the reference buffer resulting in 2.048v on refcomp. if refin is tied high, the reference buffer is disabled and refcomp can be tied to refout to achieve a 2.5v span or driven with an external reference or dac. table 3 summarizes the reference modes. table 3. reference mode table mode refin refcomp refin tied low 0v input 2.048v output refin is buffer input 1v to 2.6v input 1.6384v to 4.26v output (1.6384 ? refin) refin tied high 5v input input, 19.2k w to ground full scale and offset in applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero during a calibration sequence. offset error must be adjusted before full-scale error. zero offset is achieved by adjusting the offset applied to the C input. for single-ended inputs, this offset should be applied to the com pin. for differen- tial inputs, the C input is dictated by the mux address. for zero offset error, apply 0.5lsb (actual voltage will vary with input span selected) to the + input and adjust the offset at the C input until the output code flickers between 0000 0000 0000 and 0000 0000 0001 for the ltc1853 and between 00 0000 0000 and 00 0000 0001 for the ltc1852. as mentioned earlier, the internal reference is factory trimmed to 2.500v. to make sure that the reference buffer gain is not compensating for trim errors in the reference, refcomp is trimmed to 4.096v with an extremely accu- rate external 2.5v reference applied to refin. likewise, to make sure that the full-scale gain trim is not compensating for errors in the reference buffer gain, the input full-scale gain is trimmed with an extremely accurate 4.096v refer- ence applied to refcomp (refin = 5v to disable the reference buffer). this allows the use of either a 2.5v reference applied to refin or a 4.096v reference applied to refcomp to achieve accurate results. full-scale errors can be trimmed to zero by adjusting the appropriate reference voltage. for unipolar inputs, an input voltage of
14 ltc1852/ltc1853 18523f fs C 1.5lsbs should be applied to the + input and the appropriate reference adjusted until the output code flick- ers between 1111 1111 1110 and 1111 1111 1111 for the ltc1853 and between 11 1111 1110 and 11 1111 1111 for the ltc1852. for bipolar inputs, an input voltage of fs C 1.5lsbs should be applied to the + input and the appropriate reference adjusted until the output code flickers between 0111 1111 1110 and 0111 1111 1111 for the ltc1853 and between 01 1111 1110 and 01 1111 1111 for the ltc1852. these adjustments as well as the factory trims affect all channels. the channel-to-channel offset and gain error matching are guaranteed by design to meet the specifica- tions in the converter characteristics table. output data format the ltc1852/ltc1853 have a 14 bit/16-bit parallel out- put. the output word normally consists of a 10-bit/12-bit conversion result data word and a 4-bit address (three address bits a2 out , a1 out , a0 out and the diff out bit). the output drivers are enabled when rd is low provided the chip is selected (cs is low). all 14/16 data output pins and busy are supplied by ov dd and ognd to allow easy interface to 3v or 5v digital logic. the data format of the conversion result is automatically selected and determined by the uni/bip input pin. if the uni/bip pin is low indicating a unipolar input span (0 C refcomp assuming pga = 1), the format for the data is straight binary with 1 lsb = fs/4096 (1mv for refcomp = 4.096v). for the ltc1853 and 1lsb = fs/ 1024 (4mv for refcomp = 4.096v) for the ltc1852. if the uni/bip pin is high indicating a bipolar input span ( refcomp/2 for pga = 1), the format for the data is twos complement binary with 1 lsb = [(+fs) C (C fs)]/ 4096 (1mv for refcomp = 4.096v). for the ltc1853 and 1lsb = [(+ fs) C (C fs)]/1024 (4mv for refcomp = 4.096v) for the ltc1852. in both cases, the code transitions occur midway between successive integer lsb values (i.e., C fs + 0.5lsb, C fs + 1.5lsb, ... C 1.5lsb, C 0.5lsb, 0.5lsb, 1.5lsb, ... fs C 1.5lsb, fs C 0.5lsb). applicatio s i for atio wu uu the three most significant bits of the data word (d11, d10 and d9 for the ltc1853; d9, d8 and d7 for the ltc1852) also function as output bits when reading the contents of the programmable sequencer. during readback, a 7-bit status word (s6-s0) containing the contents of the cur- rent sequencer location is available when rd is low. the individual bits of the status word are outlined in figure 1. during readback, the d8 to d0 pins (ltc1853) or d6 to d0 pins (ltc1852) remain high impedance irrespective of the state of rd. figure 1. readback status word unipolar transfer characteristic (uni/bip = 0) bipolar transfer characteristic (uni/bip = 1) input voltage (v) 0 fs ?1lbs output code 1111...1111 1111...1110 1111...1101 1000...0001 1000...0000 0111...1111 0111...1110 0000...0010 0000...0001 0000...0000 18523 f01a fs = v refcomp input voltage (v) fs 1lbs 0 1lbs fs ?1lbs output code 0111...1111 0111...1110 0111...1101 0000...0001 0000...0000 1111...1111 1111...1110 1000...0010 1000...0001 1000...0000 18523 f01b bipolar zero fs = v refcomp 2 single-ended/ differential bit unipolar/ bipolar bit s6 s5 a2 a0 end of sequence bit pga bit 18523 f01 a1 mux address s4 s3 s2 s1 s0
15 ltc1852/ltc1853 18523f applicatio s i for atio wu uu board layout and bypassing to obtain the best performance from the ltc1852/ ltc1853, a printed circuit board with ground plane is required. the ground plane under the adc area should be as free of breaks and holes as possible, such that a low impedance path between all adc grounds and all adc decoupling capacitors is provided. it is critical to prevent digital noise from being coupled to the analog inputs, reference or analog power supply lines. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particu- lar, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. an analog ground plane separate from the logic system ground should be established under and around the adc. pin 34 (ognd), pin 13 (gnd), pin 16 (gnd) and all other analog grounds should be connected to this single analog ground point. the bypass capacitors should also be con- nected to this analog ground plane. no other digital grounds should be connected to this analog ground plane. in some applications, it may be desirable to connect the ov dd to the logic system supply and ognd to the logic system ground. in these cases, ov dd should be bypassed to ognd instead of the analog ground plane. low impedance analog and digital power supply common returns are essential to the low noise operation of the adc and the foil width for these tracks should be as wide as possible. in applications where the adc data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion results. these errors are due to feedthrough from the microprocessor to the sucessive approximation comparator. the problem can be eliminated by forcing the microprocessor into a wait state during conversions or by using three-state buffers to isolate the adc bus. the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. the ltc1852/ltc1853 have differential inputs to mini- mize noise coupling. common mode noise on the + and C inputs will be rejected by the input cmrr. the ltc1852/ ltc1853 will hold and convert the difference between whichever input is selected as the + input and whichever input is selected as the C input. leads to the inputs should be kept as short as possible. supply bypassing high quality, low series resistance ceramic 10 m f bypass capacitors should be used. surface mount ceramic ca- pacitors such as murata grm235y5v106z016 provide excellent bypassing in a small board space. alternatively, 10 m f tantalum capacitors in parallel with 0.1 m f ceramic capacitors can be used. bypass capacitors must be lo- cated as close to the pins as possible. the traces connect- ing the pins and the bypass capacitors must be kept short and should be made as wide as possible. digital interface internal clock the a/d converter has an internal clock that eliminates the need of synchronization between the external clock and the cs and rd signals found in other adcs. the internal clock is factory trimmed to achieve a typical conversion time of 1400ns, and a maximum conversion time over the full operating temperature range of 2 m s. no external adjustments are required. the guaranteed maxi- mum acquisition time is 150ns. in addition, a throughput time of 2.5 m s and a minimum sampling rate of 400ksps is guaranteed. cs convst t 2 t 1 18523 f04 rd shdn convst t 4 18523 f03 figure 3. shdn to convst wake-up timing figure 2. cs to shdn timing
16 ltc1852/ltc1853 18523f power shutdown the ltc1852/ltc1853 provide two power shutdown modes, nap and sleep, to save power during inactive periods. the nap mode reduces the power to 2.5mw and leaves only the digital logic and reference powered up. the wake-up time from nap to active is 200ns. in sleep mode, all bias currents are shut down and only leakage current remainsabout 20 m a. wake-up time from sleep mode is much slower since the reference circuit must power-up and settle to 0.005% for full 12-bit accuracy (0.02% for full 10-bit accuracy). sleep mode wake-up time is dependent on the value of the capacitor connected to the refcomp (pin 12). the wake-up time is 10ms with the recom- mended 10 m f capacitor. shutdown is controlled by pin 47 (shdn); the adc is in shutdown when it is low. the shutdown mode is selected with pin 46 (cs); low selects nap. timing and control conversion start and data read operations are controlled by three digital inputs: convst, cs and rd. a logic 0 applied to the convst pin will start a conversion after the adc has been selected (i.e., cs is low). once initiated, it cannot be restarted until the conversion is complete. converter status is indicated by the busy output. busy is low during a conversion. if convst returns high at a critical point during the conversion it can create small errors. for the best results, ensure that convst returns high either within 400ns after the start of the conversion or after busy rises. figures 5 through 9 show several different modes of operation. in modes 1a and 1b (figures 5 and 6), cs and rd are both tied low. the falling edge of convst starts the conversion. the data outputs are always enabled and data can be latched with the busy rising edge. mode 1a shows operation with a narrow logic low convst pulse. mode 1b shows a narrow logic high convst pulse. in mode 2 (figure 7), cs is tied low. the falling edge of convst signal again starts the conversion. data outputs are in three-state until read by the mpu with the rd signal. mode 2 can be used for operation with a shared mpu databus. in slow memory and rom modes (figures 8 and 9),cs is tied low and convst and rd are tied together. the mpu starts the conversion and reads the output with the rd signal. conversions are started by the mpu or dsp (no external sample clock). in slow memory mode, the processor applies a logic low to rd ( = convst), starting the conversion. busy goes low, forcing the processor into a wait state. the previous conversion result appears on the data outputs. when the conversion is complete, the new conversion results applicatio s i for atio wu uu figure 4. cs to convst setup timing cs convst t 2 t 1 18523 f04 rd convst busy t 6 t 7 data data (n ?1) data n 18523 f05 t 5 t conv t 8 figure 5. mode 1a convst starts a conversion. data outputs always enabled (cs = rd = 0)
17 ltc1852/ltc1853 18523f applicatio s i for atio wu uu convst busy data data (n ?1) data n 18523 f06 t 13 t 6 t 6 t 7 t 8 t conv t 5 convst busy rd data t 5 t 13 t 8 t conv t 10 data n 18523 f07 t 9 t 11 t 6 t 12 figure 7. mode 2 convst starts a conversion. data is read by rd, cs = 0 t 6 t 10 t 7 t 11 t 8 rd = convst busy data data (n ?1) data (n + 1) data n data n 18523 f08 t conv figure 8. slow memory mode timing, cs = 0 convst busy data t 8 t conv 18523 f09 data (n ?1) data n t 6 t 11 t 10 figure 9. rom mode timing, cs = 0 figure 6. mode 1b convst starts a conversion, rd = cs = 0
18 ltc1852/ltc1853 18523f applicatio s i for atio wu uu ap pear on the data outputs; busy goes high releasing the processor, and the processor takes rd ( = convst) back high and reads the new conversion data. in rom mode, the processor takes rd ( = convst) low, starting a conversion and reading the previous conversion result. after the conversion is complete, the processor can read the new result and initiate another conversion. modes of operation direct address mode the simplest mode of operation is the direct address mode. this mode is selected when both the m1 and m0 pins are low. in this mode, the address input pins directly control the mux and the configuration input pins directly control the input span. the address and configuration input pins are enabled when wr is low. wr can be tied low if the pins will be constantly driven or the rising edge of wr can be used to latch and hold the inputs for as long as wr is held high. scan mode scan mode is selected when m1 is low and m0 is high. this mode allows the converter to scan through all of the input channels sequentially and repeatedly without the user having to provide an address. the address input pins (a2 to a0) are ignored but the diff, pga and uni/bip pins are still enabled when wr is low. as in the direct address mode, wr can be held low or the rising edge of wr can be used to latch and hold the information on these pins for as long as wr is held high. the diff pin selects the scan pattern. if diff is held low, the scan pattern will consist of all eight channels in succession, single-ended relative to com (ch0-com, ch1-com, ch2-com, ch3-com, ch4- com, ch5-com, ch6-com, ch7-com, repeat). at the maximum conversion rate the throughput rate for each channel would be 400ksps/8 or 50ksps. if diff is held high, the scan pattern will consist of four differential pairs (ch0-ch1, ch2-ch3, ch4-ch5, ch6-ch7, repeat). at the maximum conversion rate, the throughput rate for each pair would be 400ksps/4 or 100ksps. it is possible to drive the diff input pin while the part is in scan mode to achieve combinations of single-ended and differential inputs. for instance, if the a0 out pin is tied to the diff input pin, the scan pattern will consist of four single-ended inputs and two differential pairs (ch0-com single-ended, ch1-com single-ended, ch2-ch3 differential, ch4-com single- ended, ch5-com single-ended, ch6-ch7 differential, repeat). the scan counter is reset to zero whenever the m0 pin changes state so that the first conversion after m0 rises will be mux address 000 (ch0-com single-ended or ch0- ch1 differential depending on the state of the diff pin). a conversion is initiated by the falling edge of convst. after each conversion, the address counter is advanced (by one if diff is low, by two if diff is high) and the mux address for the present conversion is available on the address output pins (diff out , a2 out to a0 out ) along with the conversion result. program/readback mode the ltc1852 and ltc1853 include a sequencer that can be programmed to run a sequence of up to 16 locations containing a mux address and input configuration. the mux address and input configuration for each location are programmed using the diff, a2 to a0, uni/bip and pga pins and are stored in memory along with an end-of- sequence (eos) bit that is generated automatically. the six input address and configuration bits plus the eos bit can be read back by accessing the 7-bit readback status word (s6-s0) through the data output pins. the sequencer memory is a 16 7 block of memory represented by the block diagram in figure 10. figure 10. sequencer memory block diagram location 0000 diff a2 a1 a0 uni/bip pga eos location 0001 location 0010 location 1110 location 1111 18523 f10
19 ltc1852/ltc1853 18523f applicatio s i for atio wu uu the sequencer is accessed by taking the m1 mode pin high. with m1 high, the sequencer memory is accessed by taking the m0 mode pin low. this will cause busy to go low, disabling conversions during the programming and readback of the sequencer. the sequencer is reset to location 0000 whenever m1 or m0 changes state. one of these signals should be cycled prior to any read or write operation to guarantee that the sequencer will be pro- grammed or read starting at location 0000. the sequencer is programmed sequentially starting from location 0000. rd and wr should be held high, the appropriate signals applied to the diff pin, the a2 to a0 mux address pins, the uni/bip pin and the pga pin and wr taken low to write to the memory. wr going high will latch the data into memory and advance the pointer to the next sequencer location. up to 16 locations can be pro- grammed and the last location written before m0 is taken back high will be the last location in the sequence. after 16 writes, the pointer is reset to location 0000 and any subsequent writes will erase all of the previous contents and start a new sequence. the sequencer memory can be read by holding wr high and strobing rd. taking rd low accesses the sequencer memory and enables the data output pins. the sequencer should be reset to location 0000 before beginning a read operation (by applying a positive pulse to mo). the seven output bits will be available on the diff out /s6, a2 out /s5, a1 out /s4, a0 out /s3, d11/s2, d10/s1 and d9/s0 pins (ltc1853) or diff out /s6, a2 out /s5, a1 out /s4, a0 out / s3, d9/s2, d8/s1 and d7/s0 pins (ltc1852). the d8 to d0 (ltc1853) or d6 to d0 (ltc1852) data output pins will remain high impedance during readback. rd going high will return the data output pins to a high impedance state and advance the pointer to the next location. a logic 1 on the d9/s0 (d7/s0) pin indicates the last location in the current sequence but all 16 locations can be read by continuing to clock rd. after 16 reads, the pointer is reset to location 0000. when all programming and/or reading of the sequencer memory is complete, m0 is taken high. busy will come back high enabling convst and indicat- ing that the part is ready to start a conversion. sequence run mode once the sequencer is programmed, m0 is taken high. busy will also come back high enabling convst and the next falling convst will begin a conversion using the mux address and input configuration stored in location 0000 of the sequencer memory. after each conversion, the sequencer pointer is advanced by one and the mux address ( the actual channel or channels being converted, not the sequencer pointer) for the present conversion is available on the address output pins along with the con- version result. when the sequencer finishes converting the last programmed location, the sequencer pointer will return to location 0000 for the next conversion. the sequencer will also reset to location 0000 anytime the m1 or m0 pin changes state. the contents of the sequencer memory will be retained as long as power is contiuously applied to the part. this allows the user to switch from sequence run mode to either direct address or scan mode and back without losing the programmed sequence. the part can also be disabled using cs or shutdown in nap or sleep mode without losing the programmed sequence. table 5 out- lines the operational modes of the ltc1852/ltc1853. figures 11 and 12 show the timing diagrams for writing to, reading from and running a sequence. table 5 operation mode m1 m0 wr rd comments direct address 0 0 0 oe address and configuration are driven from external pins 0 0 oe address and configuration are latched on rising edge of wr or falling edge of convst scan 0 1 0 oe address is provided by internal scan counter, configuration is driven from external pins 0 1 oe configuraton is latched on rising edge of wr or falling edge of convst program 1 0 1 write sequencer location, wr low enables inputs, rising edge of wr latches data and advances to next location readback 1 0 1 read sequencer location, falling edge of rd enables output, rising edge of rd advances to next location sequence run 1 1 x oe run programmed sequence, falling edge of convst starts conversion and advances to next location
20 ltc1852/ltc1853 18523f applicatio s i for atio wu uu l0cation 0000 l0cation 0001 l0cation n l0cation 0000 l0cation 0001 l0cation n l0cation 0000 l0cation 0001 l0cation n l0cation 0000 l0cation 0001 l0cation n location 0000 location 0001 location n location n + 1 t 18 m1 convst t 20 t 17 t 16 t 14 t 23 t 23 18523 f11 t 11 t 10 t 19 t 15 t 24 t 22 t 12 wr rd diff a2 to a0 uni/bip pga m0 busy s6 to s0 hi-z hi-z d6 to d0 (ltc1852) d8 to d0 (ltc1853) figure 11. sequencer i/o
21 ltc1852/ltc1853 18523f applicatio s i for atio wu uu figure 12. programming and running a sequence l0cation 0000 l0cation 0001 l0cation 0000 l0cation 0001 l0cation 0000 l0cation 0001 l0cation 0000 l0cation 0001 l0cation 0010 l0cation 0010 l0cation 0010 l0cation 0010 data 0000 data 0001 data 0010 data 0000 t 18 m1 convst t 20 t 16 t 14 t 17 t 15 t 23 t 8 t 5 18523 f12 t 7 t 11 t 10 t 19 t 6 t 25 convert 0000 convert 0001 convert 0010 convert 0000 wr rd diff a2 to a0 uni/bip pga hi-z m0 busy diff out a2 out to a0 out d9 to d0 (ltc1852) d11 to d0 (ltc1853)
22 ltc1852/ltc1853 18523f input configuration: all 8 channels single ended to com ch0?h7: 0v to 4.096v busy diff out /s6 a2 out /s5 a1 out /s4 a0 out /s3 d11/s2 d10/s1 d9/s0 d8 d7 d6 d5 d4 d3 d2 d1 d0 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 m1 m0 shdn cs convst rd wr diff a2 a1 a0 uni/bip pga 48 36 47 46 45 44 43 42 41 40 39 38 37 ognd 34 18523 ta01 ov dd 35 gnd gnd 1.6384x refcomp 13 16 refin refout 12 11 10 2.5v 4.096v com ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 14 v dd 9 8 7 6 5 4 3 2 1 15 0.1 f v dd 5v 10 f 1 f 0.1 f 10 f 0.1 f 10 f 2.7v to v dd 5v 5v 5v convert clock output drivers data latches ref amp 8-channel multiplexer 2.5v reference internal clock ltc1853 control logic and programmable sequencer 12-bit sampling adc + ltc1853 hardwired for 8-channel single-ended scan with unipolar 0v to 4.096v operation typical applicatio s u
23 ltc1852/ltc1853 18523f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. ltc1853 hardwired for 4-channel differential scan with bipolar 1.024v operation busy diff out /s6 a2 out /s5 a1 out /s4 a0 out /s3 d11/s2 d10/s1 d9/s0 d8 d7 d6 d5 d4 d3 d2 d1 d0 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 m1 m0 shdn cs convst rd wr diff a2 a1 a0 uni/bip pga 48 36 47 46 45 44 43 42 41 40 39 38 37 ognd 34 18523 ta02 ov dd 35 gnd gnd 1.6384x refcomp 13 16 refin refout 12 11 10 2.5v 4.096v com ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 14 v dd 9 8 7 6 5 4 3 2 1 input configuration: 4 differential channels: 1.024v 15 0.1 f v dd 5v 10 f 1 f 0.1 f 10 f 0.1 f 10 f 3v to 5v 5v 5v 5v 5v convert clock output drivers data latches ref amp 8-channel multiplexer 2.5v reference internal clock ltc1853 control logic and programmable sequencer 12-bit sampling adc + + + + + u package descriptio fw48 tssop 0501 .09 ?.20 (.0035 ?.008) 0 ?8 .45 ?.75 (.018 ?.029) .17 ?.27 (.0067 ?.0106) .50 (.0197) bsc 6.0 ?6.2** (.236 ?.244) 7.9 ?8.3 (.311 ?.327) 134 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 12.4 ?12.6* (.488 ?.496) 1.20 (.0473) max .05 ?.15 (.002 ?.006) 2 48 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 47 c .10 -t- -c- millimeters (inches) dimensions do not include mold flash. mold flash shall not exceed .152mm (.006") per side dimensions do not include interlead flash. interlead flash shall not exceed .254mm (.010") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale * ** fw package 48-lead plastic tssop (6.1mm) (reference ltc dwg # 05-08-1651) typical applicatio s u
24 ltc1852/ltc1853 18523f ? linear technology corporation 2001 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com lt/tp 0802 2k ? printed in the usa u typical applicatio data buffering using two idt7202la15 1k x 9-bit fifos allows rapid collection of 1024 samples and simple inter- face to low power, low speed, 8-bit microcontrollers. data and channel information are clocked in simultaneously and read out as two bytes using read high fifo and read low fifo lines. in the event of bus contention, resistors limit peak output current. if both fifos are read completely or reset before a burst of conversions, the empty, half full, and full flags from only one fifo need to be monitored. the retransmit inputs may also be tied together. retransmit may be used to read data repeatedly, allowing a memory limited processor to perform trans- form and filtering functions that would otherwise be difficult. busy diff out /s6 a2 out /s5 a1 out /s4 a0 out /s3 d11/s2 d10/s1 d9/s0 d8 d7 d6 d5 d4 d3 d2 d1 d0 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 m1 m0 shdn cs convst rd wr diff a2 a1 a0 uni/bip pga 48 36 47 46 45 44 43 42 41 40 39 38 37 ognd 34 18523 ta03 ov dd 35 1.6384x refcomp refin refout 12 11 10 2.5v 4.096v com ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 14 v dd 9 8 7 6 5 4 3 2 1 input configuration: all 8 channels single ended to com ch0?h7: 0v to 4.096v 15 0.1 f v dd 5v 10 f gnd gnd 13 16 1 f 0.1 f 10 f 0.1 f 10 f 5v 5v 5v 5v * convert clock output drivers data latches ref amp 8-channel multiplexer 2.5v reference internal clock ltc1853 control logic and programmable sequencer 12-bit sampling adc + d8 d7 d6 d5 d4 d3 d2 d1 d0 wr ff rs d7 d6 d5 d4 d3 d2 d1 d0 2 24 25 26 27 3 4 5 6 1 8 22 13 18 18 17 16 12 11 10 9 15 21 20 23 q8 q7 q6 q5 q4 q3 q2 q1 q0 r ef hf rt xi gnd read_high_fifo high_fifo_empty high_fifo_half_full high byte_fifo_retransmit 7 14 28 0.1 f 5v 8 1k high_fifo_full_flag low_fifo_full_flag fifo_reset d8 d7 d6 d5 d4 d3 d2 d1 d0 wr ff rs 2 24 25 26 27 3 4 5 6 1 8 22 13 19 18 17 16 12 11 10 9 15 21 20 23 q8 q7 q6 q5 q4 q3 q2 q1 q0 r ef hf rt xi gnd read_low_fifo low_fifo_empty low_fifo_half_full low byte_fifo_retransmit 7 14 28 0.1 f 5v 8 1k 8-bit data bus idt7202la15 idt7202la15 up to 1024 related parts part number description comments ltc1410 12-bit, 1.25msps, 5v adc 71.5db sinad at nyquist, 150mw dissipation ltc1415 12-bit, 1.25msps, single 5v adc 55mw power dissipation, 72db sinad ltc1418 14-bit, 200ksps, single 5v adc 15mw, serial/parallel 10v ltc1419 low power 14-bit, 800ksps adc true 14-bit linearity, 81.5db sinad, 150mw dissipation ltc1604 16-bit, 333ksps, 5v adc 90db sinad, 220mw power dissipation, pin compatible with ltc1608 ltc1850/ltc1851 10-bit/12-bit, 8-channel, 1.25msps adcs pin-compatible, programmable multiplexer and sequencer

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